Application Development Process example essay topic

SDR in the handset Perhaps the most significant issue wireless-system manufacturers face is the lack of compatibility in worldwide communications standards. The lack of a universal standard requires handset manufacturers to produce multiple models with differing electronics and programming for each standard. For users, the lack of commonality means that a handset probably won't work if you are traveling internationally. Software-defined radio has the opportunity to address these problems. SDR is used to describe wireless handset systems that provide software control of a variety of modulation techniques, band operation, communications security functions, and waveform requirements of current and evolving standards over a broad frequency range. SDR handsets can be dynamically programmed to reconfigure operations for better performance, richer feature sets, new services to the end user and new business for the service provider.

SDR handsets require an operating system that can be scaled from basic operation to support complex feature sets and interactive applications. The ability to use a single OS across a handset product line, while supporting a wide range of applications reliably, has the potential to make SDR an attractive and cost-effective alternative as advanced designs incorporating 2.5- and third-generation technologies emerge into the market. The processing power required of SDR handsets makes it likely that a design would consist of multiple processors for designated purposes, including one or more DSPs for signal processing and conversion. With most Roses, the interprocess communications (IPC) between the primary processor and DSP is done with special-purpose mechanisms, such as shared memory spaces, remote procedure calls or pipes.

Because these mechanisms are typically added on or customized after the fact, they are not necessarily consistent with the performance and reliability goals of the system as a whole. One operating system that meets many of the requirements for SDR is OSE, a message-passing RTOS with a proven long-term record in telecommunications and wireless applications. Developed by OSE Systems (San Jose, Calif. ), the RTOS is based on a message-passing architecture that provides asynchronous interprocess communication and manages to deliver and buffer ownership as messages are passed from process to process. The RTOS is not the entire story, however.

An RTOS and its associated tools should also support the application development process needed to implement features on the handset. An effective development tool chain consists of industry-standard compilers and debuggers, powerful host-target tools and accurate simulators, all supported by a comprehensive integrated development and debugging environment. SDR in the basestation Basestation design consists of the usual building blocks: radio, converters, baseband processing and control. Partitioning of these functions depends on the wireless standard.

For 2/2.5 G systems, the typical architecture consists of a multichannel front end, wideband RF and converters, followed by digital receive / transmit processors and a DSP. With the higher processing demands imposed by 3 G systems, the baseband processing could be implemented with a variety of technologies. These range from ASIC, FPGA, a combination of DSP and FPGA, and different forms of programmable application-specific standard products all the way to fully programmable DSPs. The differences among them are in cost per channel, power efficiency, development time, flexibility and ease of programming verification, ultimately resulting in different costs.

In addition to high computational capability, a software-based solution should have sufficient memory and I / O bandwidth and should be able to work seamlessly in a multiprocessor environment. In a traditional approach an ASIC or FPGA is used for chip-rate processing. In the case of a mixture of voice (high chip rate, low symbol rate) and data channels (lower chip rate, high symbol rate), the traditional approach is designed for the worst-case scenario as a hard-partitioned system. But a software-based solution can dynamically shift the processing load. Further advantages of using a programmable DSP in a basestation extend to flexible scheduling, de spreading capability, efficient distribution across multiple chips and support of advanced receiver techniques such as multiuser detectors, interference cancellation and multiple antennas.

DSP IMPLEMENTATION SPECTRUM Currently, digital systems may use a variety of components to perform DSP, ranging from application specific integrated circuits to general-purpose microprocessors. Table 1 provides a comparison of these approaches in terms of performance, power consumption, and flexibility. Note that reconfigurable hardware is very flexible because its functionality and internal structure of the device can be customized after fabrication. General-purpose processors can execute a wide variety of programs, including DSP algorithms.

However, their performance may not meet the application requirements. DSP processors include some instructions tailored for DSP computations. They generally achieve better performance than general-purpose processors, but their architecture may not be optimized for the different requirements that DSP applications may have, such as speed, power, and word length. Configurable processors have a customizable instruction set, datapath, and memory organization. Devices of this type are configured for a particular application prior to fabrication. However, each configuration requires a new compiler to generate optimal code.

In addition, the use of such a processor may be limited to a specific application. Reconfigurable hardware allows designers to change the configuration of the hardware at any time. As other researchers have recognized, this approach provides an excellent alternative for performance, power, flexibility, and fault tolerance. Users may select between different trade-offs, such as performance versus fault tolerance, depending on the application at hand.

Reconfigurable hardware, in the form of an array with multiple processing elements, presents a solution with the processing power comparable to that of hardware accelerators, with the required flexibility of a DSP. The array-based reconfigurable hardware approaches differentiate themselves in the granular ities of the processing elements. The functionality of the reconfigurable array is defined by software-based configurations, which describe the behavior of the processing elements and the routing between them. Special hardware protocols implemented in the communication and control structures of the array ensure that configurations cannot be overwritten illegally.

Furthermore, these protocols implement a unique token-based data communication between the processing elements that enable an efficient pipeline based operation. The combination of these features enables high-level programming of the array using C and a software-based simulation environment. A programming and simulation environment integrating the tool and design flows of the microcontroller / DSP and the reconfigurable hardware can thus be implemented. ASICs are optimized for a particular DSP algorithm. These devices can achieve maximum performance and minimum power consumption, but incur high development costs. Due to the cost and limited applicability of an ASIC, this approach may only be feasible for high-volume designs.

Traditional fine grain devices such as FPGAs achieve good flexibility. However, implementing basic DSP operations, such as multiplication, on an FPGA results in tremendous interconnection overhead and inefficiencies. Recently, researches have proposed coarse-grain devices that exploit the symmetry and regularity of DSP algorithms. Each cell may contain adders, multipliers, lookup tables, and other functional units. One drawback to these architectures is reduced utilization.

A DSP algorithm that requires many multipliers but few lookup tables, for example, would result in many unused functional units. In addition, the fixed number of functional units limits flexibility..