Channel Function Test example essay topic

Background and problem: The higher on the data transmission speed between the serial the ASIC chips can produce its co-channel interference (crosstalk) exponential increased. It eventually threats the ASICs' function performance or possibly pollutes their design function totally. Solution: The current crosstalk model in chip design is molded as background noise, as a Gaussian distribution. This approach is usually conservative on the throughput, and not actually represents the real distribution. In fact, the crosstalk is the nearby transmitting signals coupling onto the wireline of the receiver end.

Thus, the channel media can be modeled as a multiuse channel with a multiple inputs and single vector output (MISO). We can detect the desired signal and crosstalk signals jointly, then subtracting the crosstalk signals in receive end. Almost all the high speed data transmission interconnection between (or inside) chip has the same power spectral density, and with the simple baseband transmission. Our approach will not increase much on complexity, but significantly improve the transmission performance, especially for next generation high speed chip design. This initial draft provides an overview of the tests that will be performed on the both up-channel and downstream channel circuitry for the 6.4 Gbps HSS core on the Mistral test site.

(I) Characterization of up-channel Tx and Rx system level functional test (II) Characterization of channel performance test 1.1. Equipments and Resources Oscilloscope, Pattern Generator, Noise Generator, BERT, Specified Channel Representation Circuits, Evaluation Broad. Assist once with test setup and design software such as Lab View, building designed testbed and channel circuits. 1.2. Time Schedule and Resource Needs (beginning from 11/03) 1.2.

1. Test Bed Set Up (a) Need Pill to work with me on test bed set up in first week (11/3/03 - 11/10/03) full time. Have to a dedication 6 G test station for our testing. It will also benefit on DFE / FFE channel characteristic test. (Notice, we do not have real time scope in Fishkill.) (b) Up-channel function test: (11/11/03 - 11/24/03) full time.

Need Pill to work two days (or more) 2. Up-channel functional test 2.1. Introduction This section describes in detail the methods and planned test cases to test the up-channel functionally. The goal is to test up-channel control and status bits on register and output signals passing through debug MUX, then shown on oscilloscope between the interface of HSS TX and RX. It is know that the functional debugging often dominates the time and cost of the ASIC system development, mainly due to the limited controllability and observability of the storage elements in designs, and thus, the intermediate variables in functional specifications. Therefore, by default, many of them have been evaluated and passed in simulation test.

However, there is a necessity to test many signals in which are unable or hard to be tested in simulation, even to be re-verified on chip level testing. Most of them are control and status bits. They have been implemented as registers within Mistral. A register interface is provided to access these registers. The interface consists of control and status registers. The following sub-section describes the test cases, categorized in HSSUPCHR and HSSUPCHT. 2.2.

HSSUPCHR Signal Test Before any signals functional test, we have to first setup HSS Tx and HSS Rx. Power-On-Reset: In HSS, we can initialize it by asserting the RESET (connect to the HSS RESETOUT = '1') input high for about 200 ns (minimum of 4 reference clocks). Then the core is in the reset stat, and normal operation is suspended, also the high-speed PLL is out of lock. Waiting until RESETOUT = '0' and PRT READY = '1'. The core will go into the run state, ready to transfer data. HSS Tx and Rx setup: As mentioned in the above section, writing a register interface is provided to access specified register.

We have to select FFE 4 mode, transmit power, applying FFE 4 coefficient and AGC power values, and enable up-channel packets in HSS Tx side. On HSS Rx side, we will write / or do not write the enable up-channel bit depended on what kind of tests we will pursue. As the address enable (one bit) is asserted, the five address bits are decoded, and the register contents corresponding that address are placed on the output data bus. However, if it is not asserted, (or address is not valid), the read of registers will not have all the bits implemented, and return a zero vale in the non-implemented bit positions. GAPLENGTH: Gap Length, it is used to program the duration of the gaps as "0" = 960 ns and "1" = 1920 ns. (at maximum 6.4 Gbit /'s rate) NORESP: no response Making a register bit write of "0" or "1" on GAPLENGTH as control signal to HSSUPCHR side, test in the Recognition Phase. We will enable HSS Tx up-channel packets, and do not enable HSS Rx up-channel packets address enable bit.

This is a downstream one way transmission. Asserted "UP STRT" (register bit write on HSSUPCHR side), and stay high. It should no response from HSSUPCHT (not enable register), which will read NORESP = '1', a status register bit output (through debug MUX to oscilloscope). It will have repeated gaps and PRB S 7 pattern bursts. We can measure the gap length by connecting HSS transmitter cable to the oscilloscope, corresponding to the GAPLENGTH setting. FIXDPLEN, PATLENGTH: fixed pattern length, when FIXDPLEN set to '0', it changes the burst length.

DISPWRC We test FIXDPLEN in Coefficient Adjust Phase. After HSS set up, and assert UPSTART, we have write control signals such as FIXDPLEN = '1' and PATLENGTH = "11" (constant 81.92 us burst length) as configuration in control register, then enable both HSS Tx and Rx sides up-channel packets (enable address bit on). It will follow with Recognition Phase and Power Adjust Phase (with / or without asserting DISPWRC in HSSUPCHT side register). We can exam the burst size on the oscilloscope, followed with that pattern of these phases. When it is in the beginning phase of Coefficient Adjust, the HSSUPCHT side register should read the DFE FREEZE bit. We change the HS SCHR side register write to FIXDPLEN = '0' and PATLENGTH = "00", "01", "10" and "11", then examining the burst size on the oscilloscope accordingly.

CRCERR: CRC error CRCERRCT: CRC Error Count It is the output signal on HSSUPCHR. It can be done together with performance test in the following section with the channel injected with large white noise into channel (at point B). The channel will become severe AGON channel, having bad BER. Most likely, when the up-channel Tx packets (UPDATE) transmit to HSSUPCHR packet reception, we will read CRCERR = "1' from the register. Also, we will read CRCERRCNT from the status register as well.