Data Path Control Fsm example essay topic
419 words
Engineering Plans 312 Final Project 11/7/04 Names We plan to implement the basic multi-cycle processor design as shown in the textbook, as well as pipe lining and "jump and link". The toughest part of this design will be the data path control, for which we will be using a FSM. The ALU will implement add, sub, and, or, sell, and set functions - though a separate block is typically used for shift operations, we felt that putting sell and sr l in the ALU would simplify our design. All other basic functions (lw, sw, lui, be, be, j) will be implemented as show in the textbook. The processor will have two main stages: load instructions into memory and execute instructions. Special instruction codes will be defined as "stall" and "stop execution" to work in conjunction with the FSM. The global reset will set all memory and registers to 0, and put the FSM in "load instructions mode". We would like to use one memory module to store both instructions and data (with instructions starting at 0 and going up, and memory starting at the highest address and going down), however this design would present some addressing headaches so we will most likely use separate memory modules for instructions and data. The main part of the pipe lining implementation will be the hazard detection unit.
We plan to have this work independent of the data path control FSM as so to simplify FSM design. The hazard detection unit will control mules to drive register forwarding and will issue stall instructions directly to the instruction register when needed". Jump and link" will make use of a specially designated register (most likely one of the upper registers, since those aren't used in the provided test function). Mules will be used to feed the PC+4 into the reg file and the reg file output into the PC register.
The data path control FSM will control these mules. Please see attached sheet for breakdown of tasks, task assignments, and schedule. We will assign the later tasks in the project based on who finishes their tasks first and is ready to take on more work. Two changes to the schedule as it's attached: Daniel, not Jon, will be responsible for register file creation.
Also, design of the hazard detection unit was left off the schedule. It will be designed in parallel with the data path control FSM.
